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Alif Semiconductor /AE302F80F5582AE_CM55_HE_View /DSI /DSI_LPCLK_CTRL

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Interpret as DSI_LPCLK_CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PHY_TXREQUESTCLKHS)PHY_TXREQUESTCLKHS 0 (AUTO_CLKLANE_CTRL)AUTO_CLKLANE_CTRL

Description

Clock Lane Power Control Register

Fields

PHY_TXREQUESTCLKHS

This bit controls the D-PHY PPI TXREQUESTCLKHS signal.
AUTO_CLKLANE_CTRL

This bit enables the automatic mechanism to stop providing clock in the clock lane when time allows.

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Register License

THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ALIF SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data